EVAL-AD7328CB【PDF 29/36 页】8-Channel, Software-Selectable True Bipo

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AD7328

AUTOSHUTDOWN MODE

(PM1 = 1, PM0 = 0)

Rev. A | Page 29 of 36

AUTOSTANDBY MODE

(PM1 = 0, PM0 =1)

Once the autoshutdown mode is selected, the AD7328 auto-

matically enters shutdown on the 15

autoshutdown mode, all internal circuitry is powered down.

The AD7328 retains information in the registers during

autoshutdown. The track-and-hold is in hold mode during

autoshutdown. On the rising CS edge, the track-and-hold,

which was in hold during shutdown, returns to track as the

AD7328 begins to power up. The time to power-up from auto

shutdown is 500 μs.

In autostandby mode, portions of the AD7328 are powered

down, but the on-chip reference remains powered up. The

reference bit in the control register should be 1 to ensure that

the on-chip reference is enabled. This mode is similar to auto-

shutdown but allows the AD7328 to power up much faster,

which allows faster throughput rates.

SCLK rising edge. In

As is the case with autoshutdown mode, the AD7328 enters

standby on the 15

SCLK rising edge once the control register is

updated (see Figure 50). The part retains information in the

registers during standby. The AD7328 remains in standby until

it receives a

CS rising edge. The ADC begins to power up on the

rising edge. On the

rising edge, the track-and-hold,

which was in hold mode while the part was in standby, returns

to track.

When the control register is programmed to transition to

autoshutdown mode, it does so on the 15

Figure 50 shows the part entering the autoshutdown mode.

Once in autoshutdown mode, the CS signal must remain low to

keep the part in autoshutdown mode. The AD7328 automatically

begins to power up on the CS rising edge. The t

POWER-UP

required before a valid conversion, initiated by bringing the CS

signal low, can take place. Once this valid conversion is

complete, the AD7328 powers down again on the 15

SCLK

rising edge. The CS signal must remain low again to keep the

part in autoshutdown mode.

SCLK rising edge.

The power-up time from standby is 700 ns. The user should

ensure that 700 ns have elapsed before bringing CS low to

attempt a valid conversion. Once this valid conversion is

complete, the AD7328 again returns to standby on the 15

SCLK rising edge. The CS signal must remain low to keep the

part in standby mode.

Figure 50 shows the part entering autoshutdown mode. The

sequence of events is the same when entering autostandby mode.

In Figure 50, the power management bits are configured for auto-

shutdown. For autostandby mode, the power management bits,

PM1 and PM0, should be set to 0 and 1, respectively.

SCLK

SDATA

DIN

VALID DATA

DATA INTO CONTROL REGISTER

POWER-UP

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PM1 = 1, PM0 = 0

PART ENTERS SHUTDOWN MODE

ON THE 15TH RISING SCLK EDGE

AS PM1 = 1, PM0 = 0

PART BEGINS TO POWER

UP ON CS RISING EDGE

THE PART IS FULLY POWERED UP

ONCE

POWER-UP

HAS ELAPSED

Figure 50. Entering Autoshutdown/Autostandby Mode

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